1. Field of the Invention
The present invention relates to the field of electronic circuit packaging, and more particularly, to the field of hermetically sealed electronic circuit packaging.
2. Background Information
Hermetically sealed packages have long been used to package semiconductor devices for use in high reliability systems and in hostile environments. A primary advantage of a hermetically sealed package for a sensitive electronic device or circuit is that the hermetic seal ensures that no outside contaminants or other deleterious materials can reach the sensitive device, component or circuit. This ensures that a device which, after hermetic sealing, meets specifications during testing will not deteriorate as a result of contamination or the introduction of other deleterious materials. This assurance is particularly important in systems which must exhibit a high reliability such as implanted medical electronic devices such as pacemakers, safety and emergency related electronic systems, electronic systems for use in space satellites where the system is inaccessible and horrendously expensive to replace and in other environments as may be considered desirable.
At one time, such high reliability systems, although complex for their time, were relatively small by today's standards and were fabricated from a relatively small number of electronic devices or integrated circuits, each of which was hermetically sealed in its own container. These hermetically sealed containers were then interconnected using printed circuit boards or other similar structures. When it was felt necessary to hermetically enclose the overall system, that assembled system was enclosed within a further hermetically sealed enclosure. Such large hermetic enclosures are expensive to fabricate and seal, encompass a substantial volume and have a substantial weight. The problem of weight is particularly severe with systems which have to meet military standard 883 for hermeticity because the preparation for the fine leak test requires the application of from 45 to 75 pound per square inch (psi) (3 to 5 atmospheres) of helium pressure to ensure that helium will infiltrate any unsealed areas. This pressure is sufficient to crush or collapse any can or lid having a significant surface area, if it is not strongly reinforced or of substantial thickness. Consequently, the strength and weight of hermetic cans increase disproportionately faster with increasing size in order to prevent them for being crushed during leak testing. This is a particular problem with circuit boards which are four inches square and larger.
One means of reducing the size and weight of such hermetically sealed systems was to mount packageless chips and integrated circuits on a circuit board and rely on the overall system hermetic enclosure to protect those chips. This resulted in some weight saving and some size saving in the overall hermetic enclosure.
Unfortunately, as electronic systems have continued to become more complex and require more chips for their fabrication, the penalties associated with hermetically enclosing a system in an overall hermetic can or enclosure have grown accordingly. It has also become important to make them more compact for a variety of reasons. Among these reasons are the need to fit electronic systems into relatively small spaces without adding substantial weight to the piece of equipment of which they form a part. Further, as mechanical systems have become more dependent on electronics for their implementation and control, more electronic systems tend to be incorporated within a given piece of equipment. Consequently, in order to keep the equipment compact, it has become important that the electronic equipment be packaged in as small and efficient a manner as possible.
While the production of a container for an electronic circuit which can be hermetically sealed does not seem, at first glance, to be a particularly complicated process, this initial perception can be misleading, especially when a new can configuration is required. Lead times for the fabrication of a new container configuration normally run at least 4-6 months and often run more. If changes are required the same period of time is needed for revisions. Consequently, when a new system is being designed, it must either be designed to fit into an existing hermetic enclosure or substantial lead time must be provided for the design and fabrication of the hermetic enclosure for that system.
The high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inch long by 2 inch wide by 0.050 thick. Even more important, this interconnect structure can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where as many as 50 chips having a cost of as much as $2,000.00, each, may be incorporated in a single system on one substrate. This repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuit and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; and U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al. Each of these patents and patent applications is incorporated herein by reference.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This is done by starting with a bare substrate having a uniform thickness and the desired size. Laser milling is then used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the substrate surrounding the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C.) depending on the formulation used and then cooled to thermoplastically bond the individual components to the cavity. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E. I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pretreated to promote adhesion and coated on one side with the ULTEM.RTM. polyetherimide resin or other thermoplastic and laminated across the top of the chips, other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with contact pads on the electronic components to which it is desired to make contact. A metallization layer is deposited over the Kapton.RTM. layer. This metallization extends into the via holes and makes electrical contact to contact pads disposed thereunder. This metallization layer may be patterned in the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process.
Additional dielectric and metallization layers are provided as required in order to provide the desired interconnection pattern. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the above-identified patents and applications.
In this manner, the entire interconnect structure can be fabricated from start to finish (after receipt of the electronic components) in as little as .apprxeq.8-12 hours.
While this high density interconnect structure makes it feasible to fabricate and test complex electronic systems in much smaller packages than was previously achievable, where hermetic sealing of the package is required, the entire package must be separately enclosed in a hermetically sealed container. This substantially increases both the size and weight of the final electronic system.
It would therefore be desirable to provide a technique for hermetically enclosing a high density interconnect structure in a more efficient, more compact, lighter weight, shorter lead time manner.
This high density interconnect structure provides many advantages. Included among these are the fact that it results in the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require the prepackaging of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities are provided in an already fired ceramic substrate by laser milling. This milling process is straightforward and fairly rapid with the result that once a desired configuration for the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips can be as short as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate may begin. First, the chips are mounted on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and in the event of a high priority rush, could be completed in four hours. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than required with other packaging techniques.
Accordingly, there is a need for a hermetic enclosure for a high density interconnect structures and other structures which exhibits the qualities of compactness, lightness and reliableness which will still withstand hermeticity test conditions and still be inexpensive and easy to fabricate.